Perancangan dan Simulasi Sistem Kompresi Suara dengan Transformasi DCT

Abstract

This paper discuss design of sound compression system using VHDL syntax, XACT tools step 6.0, Xilinx Inc. and Proseries View Logic System. This process covered entry design, simulation by functionally or static clock. The compression system using the maximum clock frequency 2,8 MHz. The simulation result of clock system has maximum delay 44,5 ns. The compression result close to optimum value.

Keywords: sound compression, DCT transformation, VHDL.